This application claims the benefit of Korean Patent Application No. 2003-67913 filed on Sep. 30, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method and circuit for controlling an activation time of a column selection line signal that depends on a type of operation mode.
2. Description of the Related Art
To increase operating speed of a semiconductor memory device, operating speed of a Central Processing Unit (CPU) must be increased and the CPU should operate without a standby time, thus minimizing time required to access memory.
These requirements have resulted in development of Synchronous Dynamic Random Access Memory (SDRAM) in which memory access is made in synchronization with a system clock, thus remarkably shortening memory access time.
In general, the SDRAM operates in response to a pulse signal. The pulse signal is generated in a Single Data Rate (SDR) mode or a Double Data Rate (DDR) mode, using transitions of the system clock.
In the SDR mode, a pulse signal is generated at a rising edge or a falling edge of the system clock. In the DDR mode, a pulse signal is generated at both the rising edge and falling edge of the system clock.
The DDR mode can be classified as a DDR1 mode or a DDR2 mode. In the DDR1 mode, two items of data are read during a clock period and the two read data items are output during a clock period.
In the DDR2 mode, four items of data are read during a clock period and the four read data items are output over two clock periods. The DDR2 mode is referred to as a 4-bit prefetch mode.
Since read data is output over two clock periods in the DDR2 mode, a Column Address Strobe (CAS)-to-CAS Delay (CCD) of the DDR2 mode is prescribed to be twice the clock period, i.e., 2tCK, in the Joint Electron Device Engineering Council (JEDEC) specification.
Here, CCD denotes a time interval between two received commands. CCD=2tCK denotes that a subsequent command can only be received two clock periods after receipt of a current command, e.g., a read command.
A semiconductor memory device that operates in the DDR2 mode operates in the SDR mode in a test operation mode. In this case, CCD is preferably readjusted to 1tCK so as to reduce test time.
FIG. 1 is a timing diagram illustrating a conventional method of controlling generation of a column selection line signal CSL in the DDR2 mode. Referring to FIG. 1, a read command RC is received in response to a rising edge of an external clock signal ECLK, and a next read command RC is received in response to a rising edge of the external clock signal ECLK after two clock periods. That is, CCD=2tCK.
A first clock signal PCSLEB is activated (1) in response to at a rising edge of the external clock signal ECLK. The first clock signal PCSLEB is activated at a logic low level and becomes deactivated after a predetermined period.
The column selection line signal CSL is activated (2) at a logic high level in response to the activation of the first clock signal PCSLEB. Then, a second clock signal PCSLDB is activated (3) in response to a next rising edge of the external clock signal ECLK. The second clock signal PCSLDB is also activated at a logic low level and becomes deactivated after a predetermined period. The column selection line signal CSL is deactivated (4) in response to the activation of the second clock signal PCSLDB.
That is in the DDR2 mode, the column selection line signal CSL is activated in response to the activation of the first clock signal PCSLEB and is deactivated in response to the activation of the second clock signal PCSLDB. However, in the test mode that is the SDR mode, the read command RC is received over a period of the external clock signal ECLK, and therefore, an activation time of the column selection line signal CSL must be adjusted.
FIG. 2 is a timing diagram illustrating a conventional method of controlling generation of a column selection line signal CSL in the test operation mode. Referring to FIG. 2, a read command RC is received at a rising edge of an external clock signal ECLK and a next read command RC is received at a rising edge of the external clock signal ECLK after a clock period. That is, CCD=1tCK in the test operation mode.
A first clock signal PCSLEB is activated (1) in response to a rising edge of the external clock signal ECLK. The first clock signal PCSLEB is activated at a logic low level and becomes deactivated after a predetermined period. The column selection line signal CSL is activated (2) at a logic high level in response to the activation of the first clock signal PCSLEB.
A second clock signal PCSLDB is activated (3) in response to a next rising edge of the external clock signal ECLK. The second clock signal PCSLDB is activated (3) a shorter period after the activation of the first clock signal PCSLEB than the second clock signal PCSLDB of FIG. 1.
The second clock signal PCSLDB becomes deactivated after a predetermined period. The column selection line signal CSL is deactivated (5) when the second clock signal PCSLDB is activated.
The first clock signal PCSLEB is activated in response to the rising edge of the external clock signal ECLK that activates the second clock signal PCSLDB (4).
The activation of the second clock signal PCSLDB is accelerated for fast deactivation of the column selection line signal CSL in FIG. 2. To accelerate the activation of the second clock signal PCSLDB, control logic for controlling the second clock signal PCSLDB is required in the test operation mode.
FIG. 3 is a timing diagram illustrating another conventional method of controlling generation of a column selection line signal CSL in the test operation mode. Referring to FIG. 3, a read command RC is received at a rising edge of an external clock signal ECLK and a next read command RC is received at a rising edge of the external clock signal ECLK after a clock period. That is, CCD=1tCK in the test operation mode.
A first clock signal PCSLEB is activated (1) at a logic low level in response to a rising edge of an external clock signal ECLK and becomes deactivated at a logic high level after a predetermined time. The column selection line signal CSL is activated at a logic high level in response to the activation of the first clock signal at the low level.
A second clock signal PCSLDB is activated (3) in response to a falling edge of the external clock signal ECLK. The second clock signal PCSLDB is activated a shorter period after the activation of the first clock signal PCSLEB than the second clock signal PCSLDB of FIG. 1.
The second clock signal PCSLDB activated at the low level becomes deactivated after a predetermined time. The column selection line signal CSL is deactivated in response to the activation of the second clock signal PCSLDB.
The first clock signal PCSLEB is activated (5) at a next rising edge of the next external clock signal ECLK.
An additional buffer is required to activate (6) the second clock signal PCSLDB at a falling edge of the external clock signal ECLK as shown in FIG. 3. However, inclusion of the buffer increases the size of a semiconductor memory device, thus increasing power consumption.
Also, when the time when the second clock signal PCSLDB is activated is adjusted as shown in FIG. 2, the instants in time at which the second clock signal PCSLDB is activated become largely different in the DDR2 mode, which is a normal operation mode, and the test operation mode, thus causing an inconsistency in the activation of the second clock signal PCSLDB.